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ASIC & FPGA Development Systems

ASIC Development Systems based upon Xilinx

ET3000K10S

The ET3000K10S is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The ET3000K10S can be hosted in 32/64-bit PCI/PCIX slot, or can be used stand-alone. A ET3000K10S can emulate up to 500,000 gates of logic as measured by LSI. The ET3000K10S achieves high gate density and allows for fast target clock frequencies by utilizing Xilinx's VirtexII family for logic and memory.

TECHNICAL SPECIFICATIONS

  • Single FPGA Virtex II
  • 32/64-bit, +3.3V, PCI/PCIX-based PWB with one Xilinx VirtexII(tm) FPGA's (FF1152 BGA)
  • Initial availability: 2V6000/2V8000/2V4000
  • Flexible, abundant and configurable embedded memory:
    • Up to 331 Kb dual-port SelectRAM (assuming XC2V6000)
    • Plus up to 135 Kb Distributed RAM (assuming XC2V6000)
  • Fast/Easy FPGA configuration via standard SmartMedia FLASH card
  • Microprocessor controlled RS232 port for configuration/operational status and control
  • Fastest possible configuration using SelectMap
  • Sanity checking programs for bit files eases configuration hassles
  • 5A on-board linear regulator for +3.3V and +1.5V
    • Standalone operation via separate power connector
    • +3.3V not needed on backplane
  • 6 low skew clocks distributed to FPGA and test connectors:
    • 2 CY7B993/4 RoboClockII PLL's
    • 2 socketed oscillators
    • PCI Clock
    • 1 dividable clock via CPLD
  • Direct Support for Synplicity's Certify TDM interconnect multiplexing
  • Robust observation/debug with 450+ connections for logic analyzer observability or for pattern generator stimulus
  • Status LED's
  • User designed daughter PWB for custom circuitry and interfaces
  • HW locking mechanisms for IP protection via CPLD
  • Hosted in a 66/100/133 MHz PCI/PCIX slot or standalone
  • Four external memories included:
    • 3 512K x 36 Pipeline/Flowthrough SSRAM
    • 512 Mbyte SDRAM DIMM (upgradeable to 8 GB)

ASIC Prototyping Engine Xilinx Virtex II Single-Chip
ET Part#
# of
Gates (Million)
ET Part#
# of
Gates
(Million)
ET Part#
# of
Gates
(Million)
ET3K10S-04-4-1
4
ET3K10S-06-4-1
6
ET3K10S-06-6-1
6
ET3K10S-04-5-1
5
ET3K10S-06-5-1
6
ET3K10S-08-5-1
8
ET3K10S-04-6-1
6
ET3K10S-08-4-1
8
 
 

ET3000K10S
ET3000K10S
User Manual
FAQs
Board Diagram
Top-down View

CPLD Datasheet

Bitstream Encryption
• Encrypted Bitstreams
• Encryption Bug WhitePaper

VirtexII FPGA Family
• Datasheet
• Handbook
• 2v6000ES Errata
• 2v6000 Errata
• 2v8000 Errata

Berg 200-pin connector (on daughter card) Datasheet

Berg 200-pin connector Datasheet

Datasheet for acceptable SDRAM's
Micron 64MB/128MB
Micron 128MB/256MB
Micron 512MB/1GB
Legacy Electronics

Datasheet for SSRAM installed
Micron SyncBurst SRAM
Samsung K7A163600A

 


ET3000K10M

The ET3000K10M is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The ET3000K10M can be either hosted in 32/64-bit PCI/PCIX slot, or used in a stand-alone environment. A single ET3000K10 configured with five 2V6000's can emulate up to 3 million gates of logic as measured by LSI. The T3000K10M achieves high gate density and allows for fast target clock frequencies by utilizing up to five FPGA's from Xilinx's VirtexII family for logic and memory. High I/O-count, 1152-pin, flip-chip BGA packages are employed providing for abundant, fixed interconnect between FPGA's. A total of 400+ test pins are provided on the top of the PWB for logic analyzer-based debugging, or for pattern generator stimulus. Custom daughter cards can be mounted to these connectors as a means to interface the ET3000K10M to application-specific circuits. A reference 32-bit PCI target design and test bench are provided (in Verilog and VHDL) at no additional cost.

TECHNICAL SPECIFICATIONS

  • 32/64-bit, +3.3V, PCI/PCI-X based PWB
    • Available in configurations with two to five VirtexII(tm) FPGAs (FF1152 BGA)
    • Available with: 2V4000/2V6000/2V8000
    • Four 512Kx36 SSRAMS
    • One 72-Bit SDRAM DIMM (product ships with a 1 Gbyte SDRAM DIMM(PC133)
    • Tightly interconnected FPGA's facilitate the partitioning process
    • Flexible, abundant and configurable embedded memory in FPGA's:
    • Up to 1620 Kbytes dual-port Block SelectRAM (assuming 5 2V6000)
    • Up to 660 Kbytes Distributed SelectRAM (assuming 5 2V6000)
    • 10A on-board switching regulator for both +3.3V and +1.5V (Only requires +5V power)
    • Stand alone operation via separate power connector
    • Status LED's provide instant status and operational feedback
    • 2 CY7B993/4 RoboClock II PLLs
    • 2 3807 Clock Drivers
    • Fast/Easy FPGA configuration via standard SmartMedia FLASH card:
    • Microprocessor controlled (ATmega 128L)
    • RS232 port for configuration and/or operational status and control
    • Fastest possible configuration using SelectMap
    • Five 2V6000s configure in under 5 seconds
    • Sanity checking programs for bit files simplify the configuration process
    • 5 low skew clocks distributed to all FPGAs and headers (from up to 8 possible sources)
    • 2 socketed oscillators
    • PCI clock
    • 1 clock dividable via CPLD
    • 4 external clocks via ribbon cable(may be differential!)
    • Robust observation/debug with 400+ connections for logic analyzer observability and pattern generator stimulus
    • Custom daughter PWB headers for application-specific circuitry and interfaces
    • Full support for chipscope & Indentify™

ASIC Prototyping Engine Xilinx Virtex II Multi-Chip
ET Part#
# of
Gates (Million)
ET Part#
# of
Gates
(Million)
ET Part#
# of
Gates
(Million)
ET3K10M-04-4-2
8
ET3K10M-04-6-5
20
ET3K10M-08-4-4
16
ET3K10M-04-4-3
8
ET3K10M-06-4-2
8
ET3K10M-08-4-5
20
ET3K10M-04-4-4
16
ET3K10M-06-4-3
12
ET3K10M-06-6-2
8
ET3K10M-04-4-5
12
ET3K10M-06-4-4
16
ET3K10M-06-6-3
12
ET3K10M-04-5-2
20
ET3K10M-06-4-5
20
ET3K10M-06-6-4
16
ET3K10M-04-5-3
12
ET3K10M-06-5-2
8
ET3K10M-06-6-5
20
ET3K10M-04-5-4
16
ET3K10M-06-5-3
12
ET3K10M-08-5-2
8
ET3K10M-04-5-5
20
ET3K10M-06-5-4
16
ET3K10M-08-5-3
12
ET3K10M-04-6-2
8
ET3K10M-06-5-5
20
ET3K10M-08-5-4
16
ET3K10M-04-6-3
12
ET3K10M-08-4-2
8
ET3K10M-08-5-5
20
ET3K10M-04-6-4
16
ET3K10M-08-4-3
12
   

ET3000K10S
ET3000K10M
User Manual
Product Brief
FAQs
Board Diagram
Top-down View
CPLD Datasheet

Bitstream Encryption
• Encrypted Bitstreams
• Encryption Bug WhitePaper

VirtexII FPGA Family
• Datasheet
• Handbook
• 2v6000ES Errata
• 2v6000 Errata
• 2v8000 Errata

Berg 200-pin connector (on daughter card) Datasheet

Berg 200-pin connector Datasheet

Datasheet for SSRAM installed
Micron SyncBurst SRAM
Samsung K7A163600A

     

ET6000K10S

The ET6000K10S is a complete logic emulation system that enables ASIC or IP designers to prototype logic, memory, and embedded systems designs for a fraction of the cost of other solutions. The ET6000K10S can be hosted in 32/64-bit PCI/PCIX slot, or can be used standalone. A ET6000K10S can emulate up to 600,000 gates of logic as measured by LSI. In addition, the VirtexII Pro FPGA contains two 300MHz+ 405 PowerPC microprocessors, 328-556 18x18 multipliers, and more than 438 Kbytes of block RAM memory. Ten serial RocketI/O ports are provided on the top of the circuit board and can support a variety of serial communication protocols at speeds up to 3.125 GB/s, with 10 GB/s to follow. The ET6000K10S is designed for performance - all external memories run at a frequency of at least 133MHz and the FPGA internal speed is limited only by the logic within. A high I/O count, 1704-pin BGA package is employed allowing for a host of external interface features including test signals, four SSRAM's, four DDR SDRAM's, and two FLASH's. A total of 162 signals are provided via a 200-pin connector on the top of the PWB for logic analyzer-based debugging, or for pattern generator stimulus. Custom daughter cards can be mounted to this connector to interface the ET6000K10S to application-specific circuits. A reference 32-bit PCI target design and test bench is provided (in Verilog/VHDL) at no additional cost.

TECHNICAL SPECIFICATIONS

  • Boatloads of reference stuff included (FREE)
    • 32-bit target PCI design (Verilog/VHDL)
    • 32-bit master/target OpenCore PCI (Verilog)
    • SDRAM controller (Verilog/VHDL)
    • DDR SDRAM controller (Verilog/VHDL)
    • PowerPC 'Hello World'
    • UARTs, DOS-based utilities, PCI Drivers (with C code)
    • Board test(s)
    • Windows XP, ME, 2000, 98, NT LINUX, Solaris
    • 32/64-bit, +3.3V, PCI/PCIX-based PWB
    • Single VirtexII-Pro FPGA in FF1704
    • 2vp70, 2vp100, 2vp125
    • Four external independent SSRAM's
    • 512k/1M/2M x 36
    • pipeline or flowthrough
    • ZBT or non-ZBT
    • Four independent DDR SDRAM banks
    • 4 banks 32M/64M x 16
    • Two independent external FLASH memories
    • 8M/16M x 16
    • 10 High Speed serial ports
    • 1 10GigE Fiber (4 MGT's)
    • 2 HSSDC2 - Infiniband (2 MGT's)
    • 2 SATA (2 MGT's)
    • 2 SMA (2 MGT's)
    • One 200-pin high-speed connector
    • custom daughter cards
    • observation daughter cards
    • 5A onboard linear regulator for
    • +1.5V +1.5V @ Switcher Module
    • +2.5V @ 10A Switcher Module
    • Embedded 300+ MHz Harvard Architecture
    • Hardware Multiply/Divide Unit
    • Thirty-Two 32-bit General Purpose Registers
    • 16 KB 2-Way Set-Associative Instruction Cache
    • 16 KB 2-Way Set-Associative Data Cache
    • Memory Management Unit (MMU)
    • Timer Facilities
    • One dedicated external JTAG connectors for uP trace/debug
    • RS232 ports for PowerPC processor visibility
    • 2 Tx/Rx, 2 Tx only
    • Stand alone operation via separate power connector
    • +3.3V not needed on backplane
    • Fast/Easy FPGA configuration via standard SmartMedia FLASH card
    • 2vp70 configures in 1 second
    • Sanity checking programs for bit files eases configuration hassles connector:
    •2 CY7B994 RoboClockII PLL's for the best clock distribution
    • 1 FCT3805 low-skew clock driver (non PLL)
    • 2 user-selectable socketed oscillators PCI/PCI-X clock
    • 1 dividable clock via CPLD
    • Full support for embedded logic analyzers ChipScope,
    • ChipScope PRO
    •Identify™ from Synplicity
    • 162 signals for observation/debug

ASIC Prototyping Engine Xilinx Virtex II Single Chip
ET Part#
# of
Gates (Million)
ET Part#
# of
Gates
(Million)
ET6K10S-07-5-1
90
ET6K10S-07-6-1
7

ET6000K10S
ET6000K10S
User Manual
Product Brief
Board Diagram
Virtex II Pro Errata