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ASIC & FPGA Development Systems

ASIC Development Systems based upon Altera

ET5000K10S

The ET5000K10S is a complete logic emulation system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of other solutions. The ET5000K10S can be hosted in 32/64-bit PCI/PCIX slot, or can be used standalone. A ET5000K10S can emulate up to 600,000 gates of logic as measured by LSI. The T5000K10S achieves high gate density and allows for fast target clock frequencies by utilizing Altera's Stratix family of FPGA's for logic and memory. A high I/O count, 1508-pin BGA package is employed allowing for a host of features including test signals and external memory. A total of 242 signals are provided on the top of the PWB for logic analyzer-based debugging, or for pattern generator stimulus. Custom daughter cards can be mounted to these connectors as a means of interfacing the ET5000K10S to application-specific circuits. A reference 32-bit PCI target design and test bench is provided (in Verilog/VHDL) at no additional cost.

TECHNICAL SPECIFICATIONS

  • 32/64-bit, +3.3V, PCI/PCI-X based PWB
    • Single Stratix FPGA in BGA1508
    • 1S40, 1S60, 1S80
    • Four external 512K x 36 SSRAM's
    • One 72-Bit SDRAM DIMM
    • Enough addressing for up to 1 GB x 72
    • Shipped standard with a 512MB SDRAM DIMM PC133
    • Two 200-pin high-speed connectors for awesome signal integrity
    • 5A onboard linear regulator for +1.5V
    • 5A onboard switching regulator for +2.5V and Vtt
    • 10A switching regulator for +3.3V
    • Standalone operation via separate power connector +3.3V not needed on backplane
    • 324 signals for observation/debug
    • 6 low skew clocks distributed to FPGA's and test connector:
    • 2 CY7B994 RoboClockII PLL's for the best
    clock distribution
    • 1 FCT3805 low-skew clock driver (non-PLL)
    • 2 user-selectable socketed oscillators
    • PCI/PCI-X clock
    • 1 dividable clock via CPLD
    • Boatloads of reference stuff included (FREE)
    • 32-bit target PCI design (Verilog/VHDL)
    • 32-bit master/target OpenCore PCI (Verilog)
    • SDRAM controller (Verilog/VHDL)
    • DDR SDRAM controller (Verilog/VHDL)
    • SSRAM controller
    • DOS-based utilities
    • Board test
    • PCI Drivers (with C code)
    • Windows XP, ME, 2000, 98, NT
    • LINUX
    • Solaris
    • Full support for embedded logic analyzers
    • SignalTap
    • Identify™ (Bridges2Silicon)

ASIC Prototyping Engine Altera Stratix Single-Chip
ET Part#
# of
Gates (Million)
ET Part#
# of
Gates
(Million)
ET Part#
# of
Gates
(Million)
ET5K10S-04-6-1
40
ET5K10S-06-6-1
60
ET5K10S-08-6-1
80
ET5K10S-04-7-1
40
ET5K10S-06-7-1
60
ET5K10S-08-7-1
80

 

ET5000K10S
ET5000K10S
User Manual
Product Brief
Interconnection Table
Altera Stratix Errata
 

ET5000K10M

The ET5000K10M is a complete logic emulation system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of other solutions. The ET5000K10M is also applicable to algorithmic acceleration and recopnfigurable computing. The ET5000K10M can be hosted in 32/64-bit PCI/PCIX slot, or can be used standalone. A single ET500K10 configured with five 1S80s can emulate up to 3-4 million gates of logic as measured by LSI (not including memories, multipliers, and DSP functions). The T5000K10M achieves high gate density and allows for fast memory. High I/O count, 1508-pin, flip-chip BGA package are employed providing for abundant, fixed interconnect between the FPGAs. A total of 485 test pins are provided at the top of the PWB for logic analyzer-based debugging or for pattern generator stimulus. Custom daughter cards can be mounted to these connectors as a means of interfacing the ET5000K10M to application-specific circuits. A reference 32-bit PCI target design and test bench is provided (in Verilog/VHDL) at no additional cost.

TECHNICAL SPECIFICATIONS

  • 32/64-bit, +3.3V, PCI/PCI-X based PWB
  • Available in configurations with two to five Stratix EP1S80 PFGAs (1508BGA)
  • Four external 512K x 36 SSRAM's
    • Pipeline, flowthrough or ZBT
    • Supports up to 2M X 36 SSRAMs
  • One external 72-bit SDRAM DIMM
    • Ships standard with a 512 MB SDRAM DIMM (PC133)
    • Supports up to 8 GB SDRAM DIMM
  • Tightly interconnected FPGAs facilitate the partitioning process
  • Status LEDs provide instant status and operational feedback
  • Flexible, abundant and configurable embedded memory in FPGAs:
    • 4.6 MB dual-port ESB RAM blocks (assuming five 1s80s)
  • Two CY7B993/4 RoboclockII PLLs
  • Two FCT3807 Clock Drivers (non-PLL)
  • +10 A switching regulator for both +3.3V and +1.5V (only requires +5 V power)
  • Stand alone operation via separate power connector
  • Fast/Easy FPGA configuration via standard SmartMedia FLASH card
    • Microprocessor controller (ATmega128L)
    • RS232 port for configuration/operational status and control
    • Fatest possible configuration using parallel bus
    • Five EP1S80s configure in less than 5 seconds
    • Sanity checking program for bit files simplify the configuration process
  • 5 low skew clocks distributed to all FPGAs and headers (from up to 8 possible sources)
    • 2 user-selectable socketed oscillators
    • PCI/PCI-X clock
    • 1 dividable clock via CPLD
    • 4 external dlocks via ribbon cable (may be differential)
  • Robust observation/debug with 485+ connections for logic analyzer observability and pattern generator stimulus
  • Custom daughter PWB headers for application-specifi circuitry and interfaces
  • Full support for SignalTap and Identify ™

ASIC Prototyping Engine Altera Stratix Multi-Chip
ET Part#
Flip Flop Count (k)
ET Part#
Flip Flop Count (k)
ET Part#
Flip Flop Count (k)
ET5K10M-08-6-2
160
ET5K10M-08-6-5
400
ET5K10M-08-7-4
320
ET5K10M-08-6-3
240
ET5K10M-08-7-2
160
ET5K10M-08-7-5
400
ET5K10M-08-6-4
320
ET5K10M-08-7-3
240
   

 

ET5000K10M
ET5000K10M
User Manual

Product Brief
Interconnection Table
Altera Stratix Errata